RTL Design (IP Integration)

Company: Trilinear Technology
Location: Sherwood
Posted on: February 24, 2021

Job Description:

REMOTE
START: ASAP-

Senior ASIC Design Engineer

Who We Are:--a unique organization that offers premium intellectual property cores and design services from a team of highly experienced video and image processing engineers.- With deep expertise in delivering high quality video systems, We provide-ASIC, FPGA and software solutions to solve complicated customer design challenges.

Who We Want:- The ideal candidate will be creative and highly motivated.- They will know the difference between getting a job done and getting a job done properly.- Knowing the tools and how to code is not enough.- The right candidate will understand that quality matters in everything that they produce.- The candidate will be a creator and not an integrator.- They must understand how to deliver professional quality code.

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Job Responsibilities:

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• Contribute to the design and development of the next generation of IP products.
  
• Develop innovative micro-architectures
  
• Deliver high-quality RTL code using SystemVerilog
  
• Work with customers to successfully integrate our products into their designs.
  
  
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  Job Requirements:
  
  
  • 
    
  • 8+ years of industry experience in RTL development
    
  • Experience with Verilog or System-Verilog in complex IP and SOC design.
    
  • Proven track record of delivering high quality designs.
    
  • Block level and system level verification experience using bus functional models and/or verification IP.
    
  • Mentor, Cadence or Synopsys simulation tools.
    
  • Proven ability to work in a small company environment
    
    
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    Preferred Experience:
    
    
    • 
      
    • Successful tape out experience
      
    • Experience with linting tools, CDC and formal verification.
      
    • Deep knowledge of video and image processing systems
      
    • Experience with high speed SerDES interfaces
      
    • Good knowledge of video and image compression algorithms
      
      
      Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.PandoLogic. Keywords: ASIC Design Engineer, Location: Sherwood, OR - 97140

Keywords: Trilinear Technology, Portland , RTL Design (IP Integration), Other , Sherwood, Oregon