3D-IC STCO SOC Design Architect
Posted on: March 19, 2023
Job Description The future of Moore's Law: 3D-IC
Intel Teases Falcon Shores Supercomputer Processor: CPU and GPU in
One Socket - Tom's Hardware (tomshardware.com) The Role: The Design
Technology Pathfinding (DTP) organization in Design Enabling (DE)
is chartered to identify and drive key strategic initiatives in the
pathfinding of future technologies, as a holistic Design
co-optimization across the Product stack from System architecture
to silicon as we extend DTCO to STCO (System Technology
Co-Optimization). The job requires partnering and leveraging domain
experts across Intel and the EDA Eco-System. Responsibilities
include, but are not limited to the following:
- Architecture definition to establish STCO (System Technology
Co-Optimization) 3DIC prototypes across market segments. Identify
3D architecture configurations and die partition for best System
- Micro architecture, IP configuration, RTL coding, Verilog
system simulation, validation and timing analysis.
- Test Chips validation of 3DIC technology and methodology.
- Design optimization of 3D advanced silicon and package
technology features to enable strong product differentiation.
- Collaboration with the different Product teams to identify
critical product characteristics and target setting
- Development of Physical Design 3DIC construction and validation
methodology and EDA capabilities. The candidate should also exhibit
the following behavioral traits and/or skills:
- Excellent analytical and problem-solving skills.
- Strong verbal/written communication skills. Qualifications You
must possess the below minimum qualifications to be initially
considered for this position. Preferred qualifications are in
addition to the minimum requirements and are considered a plus
factor in identifying top candidates. Minimum Qualifications:
Master's degree in Electrical or Computer Engineering with 15+
years of experience in the following areas:
- Micro-architecture trade-offs and Logic design using System
- Design for Test (DFT) and Design for Debug (DFD), ATPG, MBIST,
- Pre-silicon and post-silicon validation.
- Simulation and debug experience using VCS/Verdi.
- Multiple clock domain design.
- Low-power design using UPF and clock gating.
- Synthesis and speed path debug.
- Scripting skills using a programming language such as Python,
TCL. Preferred Requirements:
- Experience with ARM-based Systems.
- 3D Silicon and 3D packaging technologies.
- Design Methodologies for optimal Performance Power Area Cost
(PPAC) in advanced technologies.
- Physical Design EDA tools, design reference/sign-off flows and
EDA vendor engagement.
- Circuit design and silicon technology. Inside this Business
Group As the world's largest chip manufacturer, Intel strives to
make every facet of semiconductor manufacturing state-of-the-art --
from semiconductor process development and manufacturing, through
yield improvement to packaging, final test and optimization, and
world class Supply Chain and facilities support.-- Employees in
the--Technology Development and Manufacturing Group--are part of a
worldwide network of design, development, manufacturing, and
assembly/test facilities, all focused on utilizing the power of
Moore's Law to bring smart, connected devices to every person on
Earth. Covid Statement Intel strongly encourages employees to be
vaccinated against COVID-19. Intel aligns to federal, state, and
local laws and as a contractor to the U.S. Government is subject to
government mandates that may be issued. Intel policies for COVID-19
including guidance about testing and vaccination are subject to
change over time. Posting Statement All qualified applicants will
receive consideration for employment without regard to race, color,
religion, religious creed, sex, national origin, ancestry, age,
physical or mental disability, medical condition, genetic
information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance. Benefits We offer a total compensation
package that ranks among the best in the industry. It consists of
competitive pay, stock, bonuses, as well as, benefit programs which
include health, retirement, and vacation. Find more information
about all of our Amazing Benefits here:
Model This role will be eligible for our hybrid work model which
allows employees to split their time between working on-site at
their assigned Intel site and off-site. In certain circumstances
the work model may change to accommodate business needs.
Keywords: Intel, Portland , 3D-IC STCO SOC Design Architect, Professions , Troutdale, Oregon
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